An inductor in electronics applications typically comprises a coil of wire that exhibits electromagnetic properties when current is run through the coil of wire. In general, an inductor can store energy in its magnetic field, and an inductor tends to resist a change in the amount of current flowing through it, for example. The inductance of an inductor is dependent upon several factors. One factor is the number of windings: the larger the number of windings, the higher the inductance. Another factor is the cross-sectional area of the coil: more area results in higher inductance. Another factor is the width of windings: a larger width results in a higher ratio of outer to inner diameter of the coil and reduced inductance. These factors also affect the parasitic capacitance and resistance of the inductor.
Inductors may be used singularly, or inductors may be used in pairs as differential inductors or transformers, as examples. In some semiconductor applications, such as RF IC's, inductors are manufactured on integrated circuits. It is desirable for circuits using on-chip (e.g., inductors manufactured on a semiconductor wafer or die) differential inductors to consume as little power as possible in order to extend battery life, for example, and for the differential inductors to produce as little noise as possible. Another important requirement for on-chip differential inductors is that they have low parasitic capacitance and that the inductance, capacitance, and resistance values of the pair of inductors are symmetric. On-chip inductors are significant components of RF IC's and are used in voltage controlled oscillators (VCO's), impedance matching networks, emitter degeneration circuits, and filters, as examples.
VCO's typically utilize differential inductors, which comprise two inductors coupled at one end to a common node or central tap. A VCO is an oscillator, wherein the control voltage controls the oscillator output frequency. Telecommunications systems such Bluetooth and GSM utilize VCO's in transceivers for controlling and switching channels, for example, for cell phone or wireless applications. Differential inductors with high inductivity, quality factor and low parasitic capacitance are needed for RF IC's such as VCO's in order to achieve low current and power consumption, low phase noise, and large tuning range for the frequency of the VCO.
FIG. 1 shows a prior art on-chip differential inductor in which all of the windings of two inductors are coplanar in one metallization layer. A single level differential inductor of this type is utilized in a VCO design described in a paper by Tiebout entitled, “A Fully Integrated 1.3 GHz VCO for GSM in 0.25 μm Standard CMOS with a Phasenoise of −142 dBc/Hz at 3 MHz Offset,” published in Proceedings 30th European Microwave Conference, Paris, October, 2000, which paper is incorporated herein by reference. In particular, see FIG. 5 of the Tiebout paper, which shows a similar design of a differential inductor as is shown in FIG. 1 of the present patent application.
In the single layer differential inductor shown in FIG. 1, a second metallization level is used for the under-crossings, which are necessary to increase the symmetry of the differential inductor. The inductor is designed for a low parasitic capacitance of the two differential inputs at terminals A and B. The inductor includes two partial inductors: inductor LA, which comprises a partial inductor disposed between terminal A and middle tap D, and inductor LB, which comprises a partial inductor disposed between B and the middle tap D. The partial inductors LA and LA are close to being symmetric and have a high coupling ratio. The middle tap D is typically coupled with a supply voltage (VDD). A prior art VCO circuit that the differential inductor shown in FIG. 1 may be used in is shown in FIG. 2, for example.
In the differential inductor design shown in FIG. 1, the difference of the diameter of the inner and outer windings of inductors LA and LB leads to a reduced coupling factor of the windings and to a reduced achievable inductivity. The ratio of resistivity to inductivity, which is responsible for the quality factor (Q factor), is therefore degraded. The Q factor is a measure of an inductor's performance characteristics and has strong influence on the performance of the RF circuit, such as power consumption and noise, for example. It is desirable to build on-chip differential inductors with high inductance, high Q factor, low capacitance and high symmetry using only a small footprint.
U.S. Pat. No. 6,759,937 B2 issued to Kyriazidou, entitled “On-chip Differential Multi-Layer Inductor,” which is incorporated herein by reference, discloses a differential inductor that is formed in two metal layers. The use of additional metal layers for shunting additional windings in parallel to the inductor windings is also disclosed. However, this differential inductor design does not achieve perfect symmetry, because the connection structure that is used to connect the partial inductors introduces an asymmetry.
In particular, in the prior art differential inductor formed in a single metallization layer shown in FIG. 1, and also with the prior art differential inductor formed in two metal layers as described in U.S. Pat. No. 6,759,937, there is a lack of symmetry due to the cross-overs of the inductors. For example, the underpasses where the windings cross each other add resistance and capacitance to one winding but not to the other. This offset is typically reduced in prior art designs by alternating the underpasses. However, the location within the inductor is unsymmetrical, e.g., one half inductor has its underpasses nearer to the middle pin or center tap, and the other one nearer to the A or B voltage input. It is desirable for the two inductors of a differential inductor to have the same value of inductance and for the windings to be symmetric regarding the resistance and capacitance (e.g., to the substrate or to other inductor windings).
Thus, what are needed in the art are improved differential inductor designs in integrated circuits.